1. Field of the Invention
The present invention relates to a contact element of a prober unit (a probe) for testing circuits of semiconductor chips on a semiconductor wafer in the manufacturing process of electronic devices including LSI. More particularly, the present invention relates to a probe assembly of a prober apparatus for use in a probing test. In the probing test, circuit terminals (pads) arranged on the semiconductor chips on a wafer are made to contact with vertical probes for collective measurement of electrical conductivity of the semiconductor chips.
2. Description of the Related Art
As the semiconductor technology advances, electronic devices have become more highly integrated and a circuit wiring area has increased in each wafer chip. Pads on each wafer chip have also increased in number, and have become more precisely arranged, whereby pad areas become smaller and pad pitches becomes narrower. The pad pitch will become as narrow as 20 μm in the near future.
Chip size packaging (CSP) becomes dominant in which a bear, non-packaged chip is mounted on a circuit board or other substrate. In fabricating the CSP, characteristics and quality of the chips should be verified at the wafer level.
In an exemplary inspection process, a contact element assembly is disposed between test equipment and pads on semiconductor chips. The contact element assembly includes needle probes each having a portion which is elastically deformable due to external force. A printed circuit board called probe card is used for electrically connecting the contact element assembly and test circuits on the semiconductor chips.
The portion of the probe card that interfaces with the test head of the test equipment should have compatibility in shape and pitches with those of the test head. At the same time, the portion of the probe card in contact with the wafer should have compatibility in shape and pitches with those of the chip pad. For this reason, each fabrication of the probe card frequently requires to design the probe card to meet the specifications of the wafer and the test head. Thus, fabrication of a probe card is a time-consuming process.
In addition to a conventional cantilever probe, several types of probes have been developed to meet requirements for testing chips with narrow pad pitches, and for collective testing of plural chips. Proposed probe cards man include: a needle probe card in which probes made of metal fine wires are arranged on a card substrate (Patent Document 1); a blade probe card in which blade-shaped probes are arranged in blocks (Patent Document 2); and a film probe unit (i.e., a probe sheet) in which parallel belt-like wirings are formed on one side of a sheet member such as an electric insulating film, and a part of the wiring is used as a probe element (Patent Document 3).
In conventional cantilever probes for inspecting one or several chips, tip portions of probes for contacting the semiconductor chip pads are narrow-pitched whereas base portion of the probes connected to a probe card are wide-pitched since the probes are arranged to radiate out. In this structure, the probes can be connected, e.g., soldered to circuit terminals of the probe card, which causes few wiring problems.
However, when pursuing a probe structure which meets requirements for testing chips with narrow pad pitches, and for collective testing of plural chips as described above, circuit wiring terminals should be arranged to correspond to the pitch of the probe arrangement, i.e., the pitch of the pads to be inspected. As a result, the probe arrangement should be closely wired.
FIG. 7 shows an example of a conventional probe card focusing on circuit wiring. The probe card includes a probe card 2 and card substrate 21. A chip 41 to be inspected is shown in a perspective view to clarify its positional relationship with the card substrate 21. Terminals 211 arranged at the periphery of the card substrate 21 interface with a test head (not shown) of test equipment. The terminals 211 include sections that have compatibility in shape and pitch with those of the test head.
Probes 301 are attached by a probe alignment fixing device 302 so as to correspond to terminal pads 42 on the chip 41 to be inspected on the wafer 4. The probe alignment fixing device 302 can be selected depending on the probe type. A cantilever probe alignment fixing device 302 may be used for directly soldering the probes 301 to the circuit board. A needle probe alignment fixing device 302 may be a fixing block having, for example, guide grooves formed thereon. A sheet probe alignment fixing device 302 may include a sheet member such as an electric insulating film having parallel belt-like wirings formed on one side thereof, and a part of the wiring is used as a probe element.
As the chips become more highly-integrated and narrow-pitched, wiring patterns at the periphery of the probe become more and more closely arranged. In order to finally distribute the wiring to peripheral terminals of the card substrate 21, the wiring substrate must be a multi-layer substrate having the wiring arranged densely at the periphery of the probe terminals. In a current practical patterning of a printed circuit board, about 128 to 160 wirings per signal layer is appropriate. For example, a circuit tester with about 1000 pins requires over 20 layers including a power supply layer, having thickness of 4.8 to 6.5 mm, and diameter of about 350 mm.
In terms of economical efficiency of a probe card and a standardized card substrate 21, a conversion wiring board 30 may be disposed between the probe card and the wafer so as to function as a complicated conversion wiring 43 which varies depending on the pad to be inspected (See Patent Document 3).
An exemplary wiring pattern near the probe terminals is shown in FIG. 8. In FIG. 8, a probe terminal 32-1 (e.g., a terminal on the probe sheet) on the conversion wiring board 30 is arranged at a μm pitch to correspond to the pad on the chip to be inspected. In order to distribute the wiring from the probe terminals in a wide-pitched pattern, the wiring is connected to a land 351a of a via hole 351 for interlayer conduction via a pattern 34-1 on a first layer 37-1 of the conversion wiring board 30. The wiring is extended from the land 351a via the via hole 351, and via conductive patterns and via holes on a second layer 37-2 and above layers of the conversion wiring board 30 to a backside layer (i.e., the layer of inspection equipment side), which is a nth layer 37-n on the conversion wiring board 30.
Similarly, wiring is extended from a probe terminal 32-2 to a land 352a of a via hole 352 via a pattern 34-2 on the first layer 37-1 of the conversion wiring board 30. The pattern is developed from the land 352a via the via hole 352, and via conductors and via holes on the second layer 37-2 and above layers on the conversion wiring board 30 to the backside layer, which is the nth layer 37-n on the conversion wiring board 30.
As described above, in order to convert the pattern wiring from the probe terminal corresponding to the chip to be inspected 41 to the wide-pitched pattern wiring using a multilayer substrate, lands of the via holes connected to each probe terminal need to be positioned near the probe terminal on the same layer.    [Patent Document 1] Japanese Patent Application Laid-Open (JP-A) No. 2006-003191    [Patent Document 2] JP-A No. 2004-340654    [Patent Document 3] JP-A No. 2001-183392
A presently common pitch of via holes and lands is, however, about 0.5 mm, which is large about 10 times as compared with a pad pitch of a chip to be inspected. When considering a pattern wiring area from a probe terminal, the land arrangement cannot be within a probe region.
If the land arrangement also include outside area of the probe region, then a multi-pinned structure is difficult to establish and collective testing of plural chips is prevented. Further, the lengths of the wirings from each of the probe terminals vary considerably to prevent impedance matching.
In view of the aforementioned, an object of the invention is to provide an inexpensive probe card which is applicable to narrow-pitched pad arrangements while addressing the problem of closely-arranged wirings near probe terminals.